rcp.h (33101B)
1 #ifndef _RCP_H_ 2 #define _RCP_H_ 3 4 /************************************************************************** 5 * * 6 * Copyright (C) 1995, Silicon Graphics, Inc. * 7 * * 8 * These coded instructions, statements, and computer programs contain * 9 * unpublished proprietary information of Silicon Graphics, Inc., and * 10 * are protected by Federal copyright law. They may not be disclosed * 11 * to third parties or copied or duplicated in any form, in whole or * 12 * in part, without the prior written consent of Silicon Graphics, Inc. * 13 * * 14 **************************************************************************/ 15 16 /************************************************************************** 17 * 18 * File: rcp.h 19 * 20 * This file contains register and bit definitions for RCP memory map. 21 * $Revision: 1.20 $ 22 * $Date: 1997/07/23 08:35:21 $ 23 * $Source: /disk6/Master/cvsmdev2/PR/include/rcp.h,v $ 24 * 25 **************************************************************************/ 26 27 #include <PR/R4300.h> 28 #include <PR/ultratypes.h> 29 30 /********************************************************************** 31 * 32 * Here is a quick overview of the RCP memory map: 33 * 34 35 0x0000_0000 .. 0x03ef_ffff RDRAM memory 36 0x03f0_0000 .. 0x03ff_ffff RDRAM registers 37 38 RCP registers (see below) 39 0x0400_0000 .. 0x040f_ffff SP registers 40 0x0410_0000 .. 0x041f_ffff DP command registers 41 0x0420_0000 .. 0x042f_ffff DP span registers 42 0x0430_0000 .. 0x043f_ffff MI registers 43 0x0440_0000 .. 0x044f_ffff VI registers 44 0x0450_0000 .. 0x045f_ffff AI registers 45 0x0460_0000 .. 0x046f_ffff PI registers 46 0x0470_0000 .. 0x047f_ffff RI registers 47 0x0480_0000 .. 0x048f_ffff SI registers 48 0x0490_0000 .. 0x04ff_ffff unused 49 50 0x0500_0000 .. 0x05ff_ffff cartridge domain 2 51 0x0600_0000 .. 0x07ff_ffff cartridge domain 1 52 0x0800_0000 .. 0x0fff_ffff cartridge domain 2 53 0x1000_0000 .. 0x1fbf_ffff cartridge domain 1 54 55 0x1fc0_0000 .. 0x1fc0_07bf PIF Boot Rom (1984 bytes) 56 0x1fc0_07c0 .. 0x1fc0_07ff PIF (JoyChannel) RAM (64 bytes) 57 0x1fc0_0800 .. 0x1fcf_ffff Reserved 58 0x1fd0_0000 .. 0x7fff_ffff cartridge domain 1 59 0x8000_0000 .. 0xffff_ffff external SysAD device 60 61 The Indy development board use cartridge domain 1: 62 0x1000_0000 .. 0x10ff_ffff RAMROM 63 0x1800_0000 .. 0x1800_0003 GIO interrupt (6 bits valid in 4 bytes) 64 0x1800_0400 .. 0x1800_0403 GIO sync (6 bits valid in 4 bytes) 65 0x1800_0800 .. 0x1800_0803 CART interrupt (6 bits valid in 4 bytes) 66 67 68 69 **************************************************************************/ 70 71 72 /************************************************************************* 73 * RDRAM Memory (Assumes that maximum size is 4 MB) 74 */ 75 #define RDRAM_0_START 0x00000000 76 #define RDRAM_0_END 0x001FFFFF 77 #define RDRAM_1_START 0x00200000 78 #define RDRAM_1_END 0x003FFFFF 79 80 #define RDRAM_START RDRAM_0_START 81 #define RDRAM_END RDRAM_1_END 82 83 84 /************************************************************************* 85 * Address predicates 86 */ 87 #if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) 88 #define IS_RDRAM(x) ((unsigned)(x) >= RDRAM_START && \ 89 (unsigned)(x) < RDRAM_END) 90 #endif 91 92 93 /************************************************************************* 94 * RDRAM Registers (0x03f0_0000 .. 0x03ff_ffff) 95 */ 96 #define RDRAM_BASE_REG 0x03F00000 97 98 #define RDRAM_CONFIG_REG (RDRAM_BASE_REG+0x00) 99 #define RDRAM_DEVICE_TYPE_REG (RDRAM_BASE_REG+0x00) 100 #define RDRAM_DEVICE_ID_REG (RDRAM_BASE_REG+0x04) 101 #define RDRAM_DELAY_REG (RDRAM_BASE_REG+0x08) 102 #define RDRAM_MODE_REG (RDRAM_BASE_REG+0x0c) 103 #define RDRAM_REF_INTERVAL_REG (RDRAM_BASE_REG+0x10) 104 #define RDRAM_REF_ROW_REG (RDRAM_BASE_REG+0x14) 105 #define RDRAM_RAS_INTERVAL_REG (RDRAM_BASE_REG+0x18) 106 #define RDRAM_MIN_INTERVAL_REG (RDRAM_BASE_REG+0x1c) 107 #define RDRAM_ADDR_SELECT_REG (RDRAM_BASE_REG+0x20) 108 #define RDRAM_DEVICE_MANUF_REG (RDRAM_BASE_REG+0x24) 109 110 #define RDRAM_0_DEVICE_ID 0 111 #define RDRAM_1_DEVICE_ID 1 112 113 #define RDRAM_RESET_MODE 0 114 #define RDRAM_ACTIVE_MODE 1 115 #define RDRAM_STANDBY_MODE 2 116 117 #define RDRAM_LENGTH (2*512*2048) 118 #define RDRAM_0_BASE_ADDRESS (RDRAM_0_DEVICE_ID*RDRAM_LENGTH) 119 #define RDRAM_1_BASE_ADDRESS (RDRAM_1_DEVICE_ID*RDRAM_LENGTH) 120 121 #define RDRAM_0_CONFIG 0x00000 122 #define RDRAM_1_CONFIG 0x00400 123 #define RDRAM_GLOBAL_CONFIG 0x80000 124 125 126 /************************************************************************* 127 * PIF Physical memory map (total size = 2 KB) 128 * 129 * Size Description Mode 130 * 1FC007FF +-------+-----------------+-----+ 131 * | 64 B | JoyChannel RAM | R/W | 132 * 1FC007C0 +-------+-----------------+-----+ 133 * |1984 B | Boot ROM | * | * = Reserved 134 * 1FC00000 +-------+-----------------+-----+ 135 * 136 */ 137 #define PIF_ROM_START 0x1FC00000 138 #define PIF_ROM_END 0x1FC007BF 139 #define PIF_RAM_START 0x1FC007C0 140 #define PIF_RAM_END 0x1FC007FF 141 142 143 /************************************************************************* 144 * Controller channel 145 * Each game controller channel has 4 error bits that are defined in bit 6-7 of 146 * the Rx and Tx data size area bytes. Programmers need to clear these bits 147 * when setting the Tx/Rx size area values for a channel 148 */ 149 #define CHNL_ERR_NORESP 0x80 /* Bit 7 (Rx): No response error */ 150 #define CHNL_ERR_OVERRUN 0x40 /* Bit 6 (Rx): Overrun error */ 151 #define CHNL_ERR_FRAME 0x80 /* Bit 7 (Tx): Frame error */ 152 #define CHNL_ERR_COLLISION 0x40 /* Bit 6 (Tx): Collision error */ 153 154 #define CHNL_ERR_MASK 0xC0 /* Bit 6-7: channel errors */ 155 156 157 /************************************************************************* 158 * External device info 159 */ 160 #define DEVICE_TYPE_CART 0 /* ROM cartridge */ 161 #define DEVICE_TYPE_BULK 1 /* ROM bulk */ 162 #define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */ 163 #define DEVICE_TYPE_SRAM 3 /* SRAM */ 164 #define DEVICE_TYPE_INIT 7 /* initial value */ 165 166 /************************************************************************* 167 * SP Memory 168 */ 169 #define SP_DMEM_START 0x04000000 /* read/write */ 170 #define SP_DMEM_END 0x04000FFF 171 #define SP_IMEM_START 0x04001000 /* read/write */ 172 #define SP_IMEM_END 0x04001FFF 173 174 /************************************************************************* 175 * SP CP0 Registers 176 */ 177 178 #define SP_BASE_REG 0x04040000 179 180 /* SP memory address (R/W): [11:0] DMEM/IMEM address; [12] 0=DMEM,1=IMEM */ 181 #define SP_MEM_ADDR_REG (SP_BASE_REG+0x00) /* Master */ 182 183 /* SP DRAM DMA address (R/W): [23:0] RDRAM address */ 184 #define SP_DRAM_ADDR_REG (SP_BASE_REG+0x04) /* Slave */ 185 186 /* SP read DMA length (R/W): [11:0] length, [19:12] count, [31:20] skip */ 187 /* direction: I/DMEM <- RDRAM */ 188 #define SP_RD_LEN_REG (SP_BASE_REG+0x08) /* R/W: read len */ 189 190 /* SP write DMA length (R/W): [11:0] length, [19:12] count, [31:20] skip */ 191 /* direction: I/DMEM -> RDRAM */ 192 #define SP_WR_LEN_REG (SP_BASE_REG+0x0C) /* R/W: write len */ 193 194 /* SP status (R/W): [14:0] valid bits; see below for write/read mode */ 195 #define SP_STATUS_REG (SP_BASE_REG+0x10) 196 197 /* SP DMA full (R): [0] valid bit; dma full */ 198 #define SP_DMA_FULL_REG (SP_BASE_REG+0x14) 199 200 /* SP DMA busy (R): [0] valid bit; dma busy */ 201 #define SP_DMA_BUSY_REG (SP_BASE_REG+0x18) 202 203 /* SP semaphore (R/W): Read: [0] semaphore flag (set on read) */ 204 /* Write: [] clear semaphore flag */ 205 #define SP_SEMAPHORE_REG (SP_BASE_REG+0x1C) 206 207 /* SP PC (R/W): [11:0] program counter */ 208 #define SP_PC_REG 0x04080000 209 210 /* SP MEM address: bit 12 specifies if address is IMEM or DMEM */ 211 #define SP_DMA_DMEM 0x0000 /* Bit 12: 0=DMEM, 1=IMEM */ 212 #define SP_DMA_IMEM 0x1000 /* Bit 12: 0=DMEM, 1=IMEM */ 213 214 /* 215 * Values to clear/set bit in status reg (SP_STATUS_REG - write) 216 */ 217 #define SP_CLR_HALT 0x00001 /* Bit 0: clear halt */ 218 #define SP_SET_HALT 0x00002 /* Bit 1: set halt */ 219 #define SP_CLR_BROKE 0x00004 /* Bit 2: clear broke */ 220 #define SP_CLR_INTR 0x00008 /* Bit 3: clear intr */ 221 #define SP_SET_INTR 0x00010 /* Bit 4: set intr */ 222 #define SP_CLR_SSTEP 0x00020 /* Bit 5: clear sstep */ 223 #define SP_SET_SSTEP 0x00040 /* Bit 6: set sstep */ 224 #define SP_CLR_INTR_BREAK 0x00080 /* Bit 7: clear intr on break */ 225 #define SP_SET_INTR_BREAK 0x00100 /* Bit 8: set intr on break */ 226 #define SP_CLR_SIG0 0x00200 /* Bit 9: clear signal 0 */ 227 #define SP_SET_SIG0 0x00400 /* Bit 10: set signal 0 */ 228 #define SP_CLR_SIG1 0x00800 /* Bit 11: clear signal 1 */ 229 #define SP_SET_SIG1 0x01000 /* Bit 12: set signal 1 */ 230 #define SP_CLR_SIG2 0x02000 /* Bit 13: clear signal 2 */ 231 #define SP_SET_SIG2 0x04000 /* Bit 14: set signal 2 */ 232 #define SP_CLR_SIG3 0x08000 /* Bit 15: clear signal 3 */ 233 #define SP_SET_SIG3 0x10000 /* Bit 16: set signal 3 */ 234 #define SP_CLR_SIG4 0x20000 /* Bit 17: clear signal 4 */ 235 #define SP_SET_SIG4 0x40000 /* Bit 18: set signal 4 */ 236 #define SP_CLR_SIG5 0x80000 /* Bit 19: clear signal 5 */ 237 #define SP_SET_SIG5 0x100000 /* Bit 20: set signal 5 */ 238 #define SP_CLR_SIG6 0x200000 /* Bit 21: clear signal 6 */ 239 #define SP_SET_SIG6 0x400000 /* Bit 22: set signal 6 */ 240 #define SP_CLR_SIG7 0x800000 /* Bit 23: clear signal 7 */ 241 #define SP_SET_SIG7 0x1000000 /* Bit 24: set signal 7 */ 242 243 /* 244 * Patterns to interpret status reg (SP_STATUS_REG - read) 245 */ 246 #define SP_STATUS_HALT 0x001 /* Bit 0: halt */ 247 #define SP_STATUS_BROKE 0x002 /* Bit 1: broke */ 248 #define SP_STATUS_DMA_BUSY 0x004 /* Bit 2: dma busy */ 249 #define SP_STATUS_DMA_FULL 0x008 /* Bit 3: dma full */ 250 #define SP_STATUS_IO_FULL 0x010 /* Bit 4: io full */ 251 #define SP_STATUS_SSTEP 0x020 /* Bit 5: single step */ 252 #define SP_STATUS_INTR_BREAK 0x040 /* Bit 6: interrupt on break */ 253 #define SP_STATUS_SIG0 0x080 /* Bit 7: signal 0 set */ 254 #define SP_STATUS_SIG1 0x100 /* Bit 8: signal 1 set */ 255 #define SP_STATUS_SIG2 0x200 /* Bit 9: signal 2 set */ 256 #define SP_STATUS_SIG3 0x400 /* Bit 10: signal 3 set */ 257 #define SP_STATUS_SIG4 0x800 /* Bit 11: signal 4 set */ 258 #define SP_STATUS_SIG5 0x1000 /* Bit 12: signal 5 set */ 259 #define SP_STATUS_SIG6 0x2000 /* Bit 13: signal 6 set */ 260 #define SP_STATUS_SIG7 0x4000 /* Bit 14: signal 7 set */ 261 262 /* 263 * Use of SIG bits 264 */ 265 #define SP_CLR_YIELD SP_CLR_SIG0 266 #define SP_SET_YIELD SP_SET_SIG0 267 #define SP_STATUS_YIELD SP_STATUS_SIG0 268 #define SP_CLR_YIELDED SP_CLR_SIG1 269 #define SP_SET_YIELDED SP_SET_SIG1 270 #define SP_STATUS_YIELDED SP_STATUS_SIG1 271 #define SP_CLR_TASKDONE SP_CLR_SIG2 272 #define SP_SET_TASKDONE SP_SET_SIG2 273 #define SP_STATUS_TASKDONE SP_STATUS_SIG2 274 #define SP_CLR_RSPSIGNAL SP_CLR_SIG3 275 #define SP_SET_RSPSIGNAL SP_SET_SIG3 276 #define SP_STATUS_RSPSIGNAL SP_STATUS_SIG3 277 #define SP_CLR_CPUSIGNAL SP_CLR_SIG4 278 #define SP_SET_CPUSIGNAL SP_SET_SIG4 279 #define SP_STATUS_CPUSIGNAL SP_STATUS_SIG4 280 281 /* SP IMEM BIST REG (R/W): [6:0] BIST status bits; see below for detail */ 282 #define SP_IBIST_REG 0x04080004 283 284 /* 285 * Patterns to interpret status reg (SP_BIST_REG - write) 286 */ 287 #define SP_IBIST_CHECK 0x01 /* Bit 0: BIST check */ 288 #define SP_IBIST_GO 0x02 /* Bit 1: BIST go */ 289 #define SP_IBIST_CLEAR 0x04 /* Bit 2: BIST clear */ 290 291 /* 292 * Patterns to interpret status reg (SP_BIST_REG - read) 293 */ 294 /* First 2 bits are same as in write mode: 295 * Bit 0: BIST check; Bit 1: BIST go 296 */ 297 #define SP_IBIST_DONE 0x04 /* Bit 2: BIST done */ 298 #define SP_IBIST_FAILED 0x78 /* Bit [6:3]: BIST fail */ 299 300 301 /************************************************************************* 302 * DP Command Registers 303 */ 304 #define DPC_BASE_REG 0x04100000 305 306 /* DP CMD DMA start (R/W): [23:0] DMEM/RDRAM start address */ 307 #define DPC_START_REG (DPC_BASE_REG+0x00) 308 309 /* DP CMD DMA end (R/W): [23:0] DMEM/RDRAM end address */ 310 #define DPC_END_REG (DPC_BASE_REG+0x04) 311 312 /* DP CMD DMA end (R): [23:0] DMEM/RDRAM current address */ 313 #define DPC_CURRENT_REG (DPC_BASE_REG+0x08) 314 315 /* DP CMD status (R/W): [9:0] valid bits - see below for definitions */ 316 #define DPC_STATUS_REG (DPC_BASE_REG+0x0C) 317 318 /* DP clock counter (R): [23:0] clock counter */ 319 #define DPC_CLOCK_REG (DPC_BASE_REG+0x10) 320 321 /* DP buffer busy counter (R): [23:0] clock counter */ 322 #define DPC_BUFBUSY_REG (DPC_BASE_REG+0x14) 323 324 /* DP pipe busy counter (R): [23:0] clock counter */ 325 #define DPC_PIPEBUSY_REG (DPC_BASE_REG+0x18) 326 327 /* DP TMEM load counter (R): [23:0] clock counter */ 328 #define DPC_TMEM_REG (DPC_BASE_REG+0x1C) 329 330 /* 331 * Values to clear/set bit in status reg (DPC_STATUS_REG - write) 332 */ 333 #define DPC_CLR_XBUS_DMEM_DMA 0x0001 /* Bit 0: clear xbus_dmem_dma */ 334 #define DPC_SET_XBUS_DMEM_DMA 0x0002 /* Bit 1: set xbus_dmem_dma */ 335 #define DPC_CLR_FREEZE 0x0004 /* Bit 2: clear freeze */ 336 #define DPC_SET_FREEZE 0x0008 /* Bit 3: set freeze */ 337 #define DPC_CLR_FLUSH 0x0010 /* Bit 4: clear flush */ 338 #define DPC_SET_FLUSH 0x0020 /* Bit 5: set flush */ 339 #define DPC_CLR_TMEM_CTR 0x0040 /* Bit 6: clear tmem ctr */ 340 #define DPC_CLR_PIPE_CTR 0x0080 /* Bit 7: clear pipe ctr */ 341 #define DPC_CLR_CMD_CTR 0x0100 /* Bit 8: clear cmd ctr */ 342 #define DPC_CLR_CLOCK_CTR 0x0200 /* Bit 9: clear clock ctr */ 343 344 /* 345 * Patterns to interpret status reg (DPC_STATUS_REG - read) 346 */ 347 #define DPC_STATUS_XBUS_DMEM_DMA 0x001 /* Bit 0: xbus_dmem_dma */ 348 #define DPC_STATUS_FREEZE 0x002 /* Bit 1: freeze */ 349 #define DPC_STATUS_FLUSH 0x004 /* Bit 2: flush */ 350 /*#define DPC_STATUS_FROZEN 0x008*/ /* Bit 3: frozen */ 351 #define DPC_STATUS_START_GCLK 0x008 /* Bit 3: start gclk */ 352 #define DPC_STATUS_TMEM_BUSY 0x010 /* Bit 4: tmem busy */ 353 #define DPC_STATUS_PIPE_BUSY 0x020 /* Bit 5: pipe busy */ 354 #define DPC_STATUS_CMD_BUSY 0x040 /* Bit 6: cmd busy */ 355 #define DPC_STATUS_CBUF_READY 0x080 /* Bit 7: cbuf ready */ 356 #define DPC_STATUS_DMA_BUSY 0x100 /* Bit 8: dma busy */ 357 #define DPC_STATUS_END_VALID 0x200 /* Bit 9: end valid */ 358 #define DPC_STATUS_START_VALID 0x400 /* Bit 10: start valid */ 359 360 361 /************************************************************************* 362 * DP Span Registers 363 */ 364 #define DPS_BASE_REG 0x04200000 365 366 /* DP tmem bist (R/W): [10:0] BIST status bits; see below for detail */ 367 #define DPS_TBIST_REG (DPS_BASE_REG+0x00) 368 369 /* DP span test mode (R/W): [0] Span buffer test access enable */ 370 #define DPS_TEST_MODE_REG (DPS_BASE_REG+0x04) 371 372 /* DP span buffer test address (R/W): [6:0] bits; see below for detail */ 373 #define DPS_BUFTEST_ADDR_REG (DPS_BASE_REG+0x08) 374 375 /* DP span buffer test data (R/W): [31:0] span buffer data */ 376 #define DPS_BUFTEST_DATA_REG (DPS_BASE_REG+0x0C) 377 378 /* 379 * Patterns to interpret status reg (DPS_TMEM_BIST_REG - write) 380 */ 381 #define DPS_TBIST_CHECK 0x01 /* Bit 0: BIST check */ 382 #define DPS_TBIST_GO 0x02 /* Bit 1: BIST go */ 383 #define DPS_TBIST_CLEAR 0x04 /* Bit 2: BIST clear */ 384 385 /* 386 * Patterns to interpret status reg (DPS_TMEM_BIST_REG - read) 387 */ 388 /* First 2 bits are same as in write mode: 389 * Bit 0: BIST check; Bit 1: BIST go 390 */ 391 #define DPS_TBIST_DONE 0x004 /* Bit 2: BIST done */ 392 #define DPS_TBIST_FAILED 0x7F8 /* Bit [10:3]: BIST fail */ 393 394 395 /************************************************************************* 396 * MIPS Interface (MI) Registers 397 */ 398 #define MI_BASE_REG 0x04300000 399 400 /* 401 * MI init mode (W): [6:0] init length, [7] clear init mode, [8] set init mode 402 * [9/10] clear/set ebus test mode, [11] clear DP interrupt 403 * (R): [6:0] init length, [7] init mode, [8] ebus test mode 404 */ 405 #define MI_INIT_MODE_REG (MI_BASE_REG+0x00) 406 #define MI_MODE_REG MI_INIT_MODE_REG 407 408 /* 409 * Values to clear/set bit in mode reg (MI_MODE_REG - write) 410 */ 411 #define MI_CLR_INIT 0x0080 /* Bit 7: clear init mode */ 412 #define MI_SET_INIT 0x0100 /* Bit 8: set init mode */ 413 #define MI_CLR_EBUS 0x0200 /* Bit 9: clear ebus test */ 414 #define MI_SET_EBUS 0x0400 /* Bit 10: set ebus test mode */ 415 #define MI_CLR_DP_INTR 0x0800 /* Bit 11: clear dp interrupt */ 416 #define MI_CLR_RDRAM 0x1000 /* Bit 12: clear RDRAM reg */ 417 #define MI_SET_RDRAM 0x2000 /* Bit 13: set RDRAM reg mode */ 418 419 /* 420 * Patterns to interpret mode reg (MI_MODE_REG - read) 421 */ 422 #define MI_MODE_INIT 0x0080 /* Bit 7: init mode */ 423 #define MI_MODE_EBUS 0x0100 /* Bit 8: ebus test mode */ 424 #define MI_MODE_RDRAM 0x0200 /* Bit 9: RDRAM reg mode */ 425 426 /* MI version (R): [7:0] io, [15:8] rac, [23:16] rdp, [31:24] rsp */ 427 #define MI_VERSION_REG (MI_BASE_REG+0x04) 428 #define MI_NOOP_REG MI_VERSION_REG 429 430 /* MI interrupt (R): [5:0] valid bits - see below for bit patterns */ 431 #define MI_INTR_REG (MI_BASE_REG+0x08) 432 433 /* 434 * MI interrupt mask (W): [11:0] valid bits - see below for bit patterns 435 * (R): [5:0] valid bits - see below for bit patterns 436 */ 437 #define MI_INTR_MASK_REG (MI_BASE_REG+0x0C) 438 439 /* 440 * The following are values to check for interrupt setting (MI_INTR_REG) 441 */ 442 #define MI_INTR_SP 0x01 /* Bit 0: SP intr */ 443 #define MI_INTR_SI 0x02 /* Bit 1: SI intr */ 444 #define MI_INTR_AI 0x04 /* Bit 2: AI intr */ 445 #define MI_INTR_VI 0x08 /* Bit 3: VI intr */ 446 #define MI_INTR_PI 0x10 /* Bit 4: PI intr */ 447 #define MI_INTR_DP 0x20 /* Bit 5: DP intr */ 448 449 /* 450 * The following are values to clear/set various interrupt bit mask 451 * They can be ORed together to manipulate multiple bits 452 * (MI_INTR_MASK_REG - write) 453 */ 454 #define MI_INTR_MASK_CLR_SP 0x0001 /* Bit 0: clear SP mask */ 455 #define MI_INTR_MASK_SET_SP 0x0002 /* Bit 1: set SP mask */ 456 #define MI_INTR_MASK_CLR_SI 0x0004 /* Bit 2: clear SI mask */ 457 #define MI_INTR_MASK_SET_SI 0x0008 /* Bit 3: set SI mask */ 458 #define MI_INTR_MASK_CLR_AI 0x0010 /* Bit 4: clear AI mask */ 459 #define MI_INTR_MASK_SET_AI 0x0020 /* Bit 5: set AI mask */ 460 #define MI_INTR_MASK_CLR_VI 0x0040 /* Bit 6: clear VI mask */ 461 #define MI_INTR_MASK_SET_VI 0x0080 /* Bit 7: set VI mask */ 462 #define MI_INTR_MASK_CLR_PI 0x0100 /* Bit 8: clear PI mask */ 463 #define MI_INTR_MASK_SET_PI 0x0200 /* Bit 9: set PI mask */ 464 #define MI_INTR_MASK_CLR_DP 0x0400 /* Bit 10: clear DP mask */ 465 #define MI_INTR_MASK_SET_DP 0x0800 /* Bit 11: set DP mask */ 466 467 /* 468 * The following are values to check for interrupt mask setting 469 * (MI_INTR_MASK_REG - read) 470 */ 471 #define MI_INTR_MASK_SP 0x01 /* Bit 0: SP intr mask */ 472 #define MI_INTR_MASK_SI 0x02 /* Bit 1: SI intr mask */ 473 #define MI_INTR_MASK_AI 0x04 /* Bit 2: AI intr mask */ 474 #define MI_INTR_MASK_VI 0x08 /* Bit 3: VI intr mask */ 475 #define MI_INTR_MASK_PI 0x10 /* Bit 4: PI intr mask */ 476 #define MI_INTR_MASK_DP 0x20 /* Bit 5: DP intr mask */ 477 478 479 /************************************************************************* 480 * Video Interface (VI) Registers 481 */ 482 #define VI_BASE_REG 0x04400000 483 484 /* VI status/control (R/W): [15-0] valid bits: 485 * [1:0] = type[1:0] (pixel size) 486 * 0: blank (no data, no sync) 487 * 1: reserved 488 * 2: 5/5/5/3 ("16" bit) 489 * 3: 8/8/8/8 (32 bit) 490 * [2] = gamma_dither_enable (normally on, unless "special effect") 491 * [3] = gamma_enable (normally on, unless MPEG/JPEG) 492 * [4] = divot_enable (normally on if antialiased, unless decal lines) 493 * [5] = reserved - always off 494 * [6] = serrate (always on if interlaced, off if not) 495 * [7] = reserved - diagnostics only 496 * [9:8] = anti-alias (aa) mode[1:0] 497 * 0: aa & resamp (always fetch extra lines) 498 * 1: aa & resamp (fetch extra lines if needed) 499 * 2: resamp only (treat as all fully covered) 500 * 3: neither (replicate pixels, no interpolate) 501 * [11] = reserved - diagnostics only 502 * [15:12] = reserved 503 * 504 */ 505 #define VI_STATUS_REG (VI_BASE_REG+0x00) 506 #define VI_CONTROL_REG VI_STATUS_REG 507 508 /* VI origin (R/W): [23:0] frame buffer origin in bytes */ 509 #define VI_ORIGIN_REG (VI_BASE_REG+0x04) 510 #define VI_DRAM_ADDR_REG VI_ORIGIN_REG 511 512 /* VI width (R/W): [11:0] frame buffer line width in pixels */ 513 #define VI_WIDTH_REG (VI_BASE_REG+0x08) 514 #define VI_H_WIDTH_REG VI_WIDTH_REG 515 516 /* VI vertical intr (R/W): [9:0] interrupt when current half-line = V_INTR */ 517 #define VI_INTR_REG (VI_BASE_REG+0x0C) 518 #define VI_V_INTR_REG VI_INTR_REG 519 520 /* 521 * VI current vertical line (R/W): [9:0] current half line, sampled once per 522 * line (the lsb of V_CURRENT is constant within a field, and in 523 * interlaced modes gives the field number - which is constant for non- 524 * interlaced modes) 525 * - Any write to this register will clear interrupt line 526 */ 527 #define VI_CURRENT_REG (VI_BASE_REG+0x10) 528 #define VI_V_CURRENT_LINE_REG VI_CURRENT_REG 529 530 /* 531 * VI video timing (R/W): [ 7: 0] horizontal sync width in pixels, 532 * [15: 8] color burst width in pixels, 533 * [19:16] vertical sync width in half lines, 534 * [29:20] start of color burst in pixels from h-sync 535 */ 536 #define VI_BURST_REG (VI_BASE_REG+0x14) 537 #define VI_TIMING_REG VI_BURST_REG 538 539 /* VI vertical sync (R/W): [9:0] number of half-lines per field */ 540 #define VI_V_SYNC_REG (VI_BASE_REG+0x18) 541 542 /* VI horizontal sync (R/W): [11: 0] total duration of a line in 1/4 pixel 543 * [20:16] a 5-bit leap pattern used for PAL only 544 * (h_sync_period) 545 */ 546 #define VI_H_SYNC_REG (VI_BASE_REG+0x1C) 547 548 /* 549 * VI horizontal sync leap (R/W): [11: 0] identical to h_sync_period 550 * [27:16] identical to h_sync_period 551 */ 552 #define VI_LEAP_REG (VI_BASE_REG+0x20) 553 #define VI_H_SYNC_LEAP_REG VI_LEAP_REG 554 555 /* 556 * VI horizontal video (R/W): [ 9: 0] end of active video in screen pixels 557 * : [25:16] start of active video in screen pixels 558 */ 559 #define VI_H_START_REG (VI_BASE_REG+0x24) 560 #define VI_H_VIDEO_REG VI_H_START_REG 561 562 /* 563 * VI vertical video (R/W): [ 9: 0] end of active video in screen half-lines 564 * : [25:16] start of active video in screen half-lines 565 */ 566 #define VI_V_START_REG (VI_BASE_REG+0x28) 567 #define VI_V_VIDEO_REG VI_V_START_REG 568 569 /* 570 * VI vertical burst (R/W): [ 9: 0] end of color burst enable in half-lines 571 * : [25:16] start of color burst enable in half-lines 572 */ 573 #define VI_V_BURST_REG (VI_BASE_REG+0x2C) 574 575 /* VI x-scale (R/W): [11: 0] 1/horizontal scale up factor (2.10 format) 576 * [27:16] horizontal subpixel offset (2.10 format) 577 */ 578 #define VI_X_SCALE_REG (VI_BASE_REG+0x30) 579 580 /* VI y-scale (R/W): [11: 0] 1/vertical scale up factor (2.10 format) 581 * [27:16] vertical subpixel offset (2.10 format) 582 */ 583 #define VI_Y_SCALE_REG (VI_BASE_REG+0x34) 584 585 /* 586 * Patterns to interpret VI_CONTROL_REG 587 */ 588 #define VI_CTRL_TYPE_16 0x00002 /* Bit [1:0] pixel size: 16 bit */ 589 #define VI_CTRL_TYPE_32 0x00003 /* Bit [1:0] pixel size: 32 bit */ 590 #define VI_CTRL_GAMMA_DITHER_ON 0x00004 /* Bit 2: default = on */ 591 #define VI_CTRL_GAMMA_ON 0x00008 /* Bit 3: default = on */ 592 #define VI_CTRL_DIVOT_ON 0x00010 /* Bit 4: default = on */ 593 #define VI_CTRL_SERRATE_ON 0x00040 /* Bit 6: on if interlaced */ 594 #define VI_CTRL_ANTIALIAS_MASK 0x00300 /* Bit [9:8] anti-alias mode */ 595 #define VI_CTRL_DITHER_FILTER_ON 0x10000 /* Bit 16: dither-filter mode */ 596 597 /* 598 * Possible video clocks (NTSC or PAL) 599 */ 600 #define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */ 601 #define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */ 602 #define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */ 603 604 605 /************************************************************************* 606 * Audio Interface (AI) Registers 607 * 608 * The address and length registers are double buffered; that is, they 609 * can be written twice before becoming full. 610 * The address must be written before the length. 611 */ 612 #define AI_BASE_REG 0x04500000 613 614 /* AI DRAM address (W): [23:0] starting RDRAM address (8B-aligned) */ 615 #define AI_DRAM_ADDR_REG (AI_BASE_REG+0x00) /* R0: DRAM address */ 616 617 /* AI length (R/W): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored */ 618 /* [17:0] transfer length (v2.0) - Bottom 3 bits are ignored */ 619 #define AI_LEN_REG (AI_BASE_REG+0x04) /* R1: Length */ 620 621 /* AI control (W): [0] DMA enable - if LSB == 1, DMA is enabled */ 622 #define AI_CONTROL_REG (AI_BASE_REG+0x08) /* R2: DMA Control */ 623 624 /* 625 * AI status (R): [31]/[0] ai_full (addr & len buffer full), [30] ai_busy 626 * Note that a 1->0 transition in ai_full will set interrupt 627 * (W): clear audio interrupt 628 */ 629 #define AI_STATUS_REG (AI_BASE_REG+0x0C) /* R3: Status */ 630 631 /* 632 * AI DAC sample period register (W): [13:0] dac rate 633 * - vid_clock/(dperiod + 1) is the DAC sample rate 634 * - (dperiod + 1) >= 66 * (aclockhp + 1) must be true 635 */ 636 #define AI_DACRATE_REG (AI_BASE_REG+0x10) /* R4: DAC rate 14-lsb*/ 637 638 /* 639 * AI bit rate (W): [3:0] bit rate (abus clock half period register - aclockhp) 640 * - vid_clock/(2 * (aclockhp + 1)) is the DAC clock rate 641 * - The abus clock stops if aclockhp is zero 642 */ 643 #define AI_BITRATE_REG (AI_BASE_REG+0x14) /* R5: Bit rate 4-lsb */ 644 645 /* Value for control register */ 646 #define AI_CONTROL_DMA_ON 0x01 /* LSB = 1: DMA enable*/ 647 #define AI_CONTROL_DMA_OFF 0x00 /* LSB = 1: DMA enable*/ 648 649 /* Value for status register */ 650 #define AI_STATUS_FIFO_FULL 0x80000000 /* Bit 31: full */ 651 #define AI_STATUS_DMA_BUSY 0x40000000 /* Bit 30: busy */ 652 653 /* DAC rate = video clock / audio frequency 654 * - DAC rate >= (66 * Bit rate) must be true 655 */ 656 #define AI_MAX_DAC_RATE 16384 /* 14-bit+1 */ 657 #define AI_MIN_DAC_RATE 132 658 659 /* Bit rate <= (DAC rate / 66) */ 660 #define AI_MAX_BIT_RATE 16 /* 4-bit+1 */ 661 #define AI_MIN_BIT_RATE 2 662 663 /* 664 * Maximum and minimum values for audio frequency based on video clocks 665 * max frequency = (video clock / min dac rate) 666 * min frequency = (video clock / max dac rate) 667 */ 668 #define AI_NTSC_MAX_FREQ 368000 /* 368 KHz */ 669 #define AI_NTSC_MIN_FREQ 3000 /* 3 KHz ~ 2971 Hz */ 670 671 #define AI_PAL_MAX_FREQ 376000 /* 376 KHz */ 672 #define AI_PAL_MIN_FREQ 3050 /* 3 KHz ~ 3031 Hz */ 673 674 #define AI_MPAL_MAX_FREQ 368000 /* 368 KHz */ 675 #define AI_MPAL_MIN_FREQ 3000 /* 3 KHz ~ 2968 Hz */ 676 677 678 /************************************************************************* 679 * Peripheral Interface (PI) Registers 680 */ 681 #define PI_BASE_REG 0x04600000 682 683 /* PI DRAM address (R/W): [23:0] starting RDRAM address */ 684 #define PI_DRAM_ADDR_REG (PI_BASE_REG+0x00) /* DRAM address */ 685 686 /* PI pbus (cartridge) address (R/W): [31:0] starting AD16 address */ 687 #define PI_CART_ADDR_REG (PI_BASE_REG+0x04) 688 689 /* PI read length (R/W): [23:0] read data length */ 690 #define PI_RD_LEN_REG (PI_BASE_REG+0x08) 691 692 /* PI write length (R/W): [23:0] write data length */ 693 #define PI_WR_LEN_REG (PI_BASE_REG+0x0C) 694 695 /* 696 * PI status (R): [0] DMA busy, [1] IO busy, [2], error 697 * (W): [0] reset controller (and abort current op), [1] clear intr 698 */ 699 #define PI_STATUS_REG (PI_BASE_REG+0x10) 700 701 /* PI dom1 latency (R/W): [7:0] domain 1 device latency */ 702 #define PI_BSD_DOM1_LAT_REG (PI_BASE_REG+0x14) 703 704 /* PI dom1 pulse width (R/W): [7:0] domain 1 device R/W strobe pulse width */ 705 #define PI_BSD_DOM1_PWD_REG (PI_BASE_REG+0x18) 706 707 /* PI dom1 page size (R/W): [3:0] domain 1 device page size */ 708 #define PI_BSD_DOM1_PGS_REG (PI_BASE_REG+0x1C) /* page size */ 709 710 /* PI dom1 release (R/W): [1:0] domain 1 device R/W release duration */ 711 #define PI_BSD_DOM1_RLS_REG (PI_BASE_REG+0x20) 712 713 /* PI dom2 latency (R/W): [7:0] domain 2 device latency */ 714 #define PI_BSD_DOM2_LAT_REG (PI_BASE_REG+0x24) /* Domain 2 latency */ 715 716 /* PI dom2 pulse width (R/W): [7:0] domain 2 device R/W strobe pulse width */ 717 #define PI_BSD_DOM2_PWD_REG (PI_BASE_REG+0x28) /* pulse width */ 718 719 /* PI dom2 page size (R/W): [3:0] domain 2 device page size */ 720 #define PI_BSD_DOM2_PGS_REG (PI_BASE_REG+0x2C) /* page size */ 721 722 /* PI dom2 release (R/W): [1:0] domain 2 device R/W release duration */ 723 #define PI_BSD_DOM2_RLS_REG (PI_BASE_REG+0x30) /* release duration */ 724 725 #define PI_DOMAIN1_REG PI_BSD_DOM1_LAT_REG 726 #define PI_DOMAIN2_REG PI_BSD_DOM2_LAT_REG 727 728 #define PI_DOM_LAT_OFS 0x00 729 #define PI_DOM_PWD_OFS 0x04 730 #define PI_DOM_PGS_OFS 0x08 731 #define PI_DOM_RLS_OFS 0x0C 732 733 /* 734 * PI status register has 3 bits active when read from (PI_STATUS_REG - read) 735 * Bit 0: DMA busy - set when DMA is in progress 736 * Bit 1: IO busy - set when IO is in progress 737 * Bit 2: Error - set when CPU issues IO request while DMA is busy 738 */ 739 #define PI_STATUS_ERROR 0x04 740 #define PI_STATUS_IO_BUSY 0x02 741 #define PI_STATUS_DMA_BUSY 0x01 742 743 /* PI status register has 2 bits active when written to: 744 * Bit 0: When set, reset PIC 745 * Bit 1: When set, clear interrupt flag 746 * The values of the two bits can be ORed together to both reset PIC and 747 * clear interrupt at the same time. 748 * 749 * Note: 750 * - The PIC does generate an interrupt at the end of each DMA. CPU 751 * needs to clear the interrupt flag explicitly (from an interrupt 752 * handler) by writing into the STATUS register with bit 1 set. 753 * 754 * - When a DMA completes, the interrupt flag is set. CPU can issue 755 * another request even while the interrupt flag is set (as long as 756 * PIC is idle). However, it is the CPU's responsibility for 757 * maintaining accurate correspondence between DMA completions and 758 * interrupts. 759 * 760 * - When PIC is reset, if PIC happens to be busy, an interrupt will 761 * be generated as PIC returns to idle. Otherwise, no interrupt will 762 * be generated and PIC remains idle. 763 */ 764 /* 765 * Values to clear interrupt/reset PIC (PI_STATUS_REG - write) 766 */ 767 #define PI_STATUS_RESET 0x01 768 #define PI_SET_RESET PI_STATUS_RESET 769 770 #define PI_STATUS_CLR_INTR 0x02 771 #define PI_CLR_INTR PI_STATUS_CLR_INTR 772 773 #define PI_DMA_BUFFER_SIZE 128 774 775 #define PI_DOM1_ADDR1 0x06000000 /* to 0x07FFFFFF */ 776 #define PI_DOM1_ADDR2 0x10000000 /* to 0x1FBFFFFF */ 777 #define PI_DOM1_ADDR3 0x1FD00000 /* to 0x7FFFFFFF */ 778 #define PI_DOM2_ADDR1 0x05000000 /* to 0x05FFFFFF */ 779 #define PI_DOM2_ADDR2 0x08000000 /* to 0x0FFFFFFF */ 780 781 782 /************************************************************************* 783 * RDRAM Interface (RI) Registers 784 */ 785 #define RI_BASE_REG 0x04700000 786 787 /* RI mode (R/W): [1:0] operating mode, [2] stop T active, [3] stop R active */ 788 #define RI_MODE_REG (RI_BASE_REG+0x00) 789 790 /* RI config (R/W): [5:0] current control input, [6] current control enable */ 791 #define RI_CONFIG_REG (RI_BASE_REG+0x04) 792 793 /* RI current load (W): [] any write updates current control register */ 794 #define RI_CURRENT_LOAD_REG (RI_BASE_REG+0x08) 795 796 /* RI select (R/W): [2:0] receive select, [2:0] transmit select */ 797 #define RI_SELECT_REG (RI_BASE_REG+0x0C) 798 799 /* RI refresh (R/W): [7:0] clean refresh delay, [15:8] dirty refresh delay, 800 * [16] refresh bank, [17] refresh enable 801 * [18] refresh optimize 802 */ 803 #define RI_REFRESH_REG (RI_BASE_REG+0x10) 804 #define RI_COUNT_REG RI_REFRESH_REG 805 806 /* RI latency (R/W): [3:0] DMA latency/overlap */ 807 #define RI_LATENCY_REG (RI_BASE_REG+0x14) 808 809 /* RI error (R): [0] nack error, [1] ack error */ 810 #define RI_RERROR_REG (RI_BASE_REG+0x18) 811 812 /* RI error (W): [] any write clears all error bits */ 813 #define RI_WERROR_REG (RI_BASE_REG+0x1C) 814 815 816 /************************************************************************* 817 * Serial Interface (SI) Registers 818 */ 819 #define SI_BASE_REG 0x04800000 820 821 /* SI DRAM address (R/W): [23:0] starting RDRAM address */ 822 #define SI_DRAM_ADDR_REG (SI_BASE_REG+0x00) /* R0: DRAM address */ 823 824 /* SI address read 64B (W): [] any write causes a 64B DMA write */ 825 #define SI_PIF_ADDR_RD64B_REG (SI_BASE_REG+0x04) /* R1: 64B PIF->DRAM */ 826 827 /* Address SI_BASE_REG + (0x08, 0x0c, 0x14) are reserved */ 828 829 /* SI address write 64B (W): [] any write causes a 64B DMA read */ 830 #define SI_PIF_ADDR_WR64B_REG (SI_BASE_REG+0x10) /* R4: 64B DRAM->PIF */ 831 832 /* 833 * SI status (W): [] any write clears interrupt 834 * (R): [0] DMA busy, [1] IO read busy, [2] reserved 835 * [3] DMA error, [12] interrupt 836 */ 837 #define SI_STATUS_REG (SI_BASE_REG+0x18) /* R6: Status */ 838 839 /* SI status register has the following bits active: 840 * 0: DMA busy - set when DMA is in progress 841 * 1: IO busy - set when IO access is in progress 842 * 3: DMA error - set when there are overlapping DMA requests 843 * 12: Interrupt - Interrupt set 844 */ 845 #define SI_STATUS_DMA_BUSY 0x0001 846 #define SI_STATUS_RD_BUSY 0x0002 847 #define SI_STATUS_DMA_ERROR 0x0008 848 #define SI_STATUS_INTERRUPT 0x1000 849 850 /************************************************************************* 851 * Development Board GIO Control Registers 852 */ 853 854 #define GIO_BASE_REG 0x18000000 855 856 /* Game to Host Interrupt */ 857 #define GIO_GIO_INTR_REG (GIO_BASE_REG+0x000) 858 859 /* Game to Host SYNC */ 860 #define GIO_GIO_SYNC_REG (GIO_BASE_REG+0x400) 861 862 /* Host to Game Interrupt */ 863 #define GIO_CART_INTR_REG (GIO_BASE_REG+0x800) 864 865 866 /************************************************************************* 867 * Common macros 868 */ 869 #if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) 870 #define IO_READ(addr) (*(vu32 *)PHYS_TO_K1(addr)) 871 #define IO_WRITE(addr,data) (*(vu32 *)PHYS_TO_K1(addr)=(u32)(data)) 872 #define RCP_STAT_PRINT \ 873 rmonPrintf("current=%x start=%x end=%x dpstat=%x spstat=%x\n", \ 874 IO_READ(DPC_CURRENT_REG), \ 875 IO_READ(DPC_START_REG), \ 876 IO_READ(DPC_END_REG), \ 877 IO_READ(DPC_STATUS_REG), \ 878 IO_READ(SP_STATUS_REG)) 879 880 #endif 881 882 #endif /* _RCP_H_ */